Two-Element Multi-Parallel-Circuit Family Satisfies Direct Fsep¶
Claim/Theorem¶
Let M_t be the binary matroid from [[multiple-parallel-classes-on-one-circuit-give-connected-cut-rank-at-least-three-family.md]] in the special case
Write
Let F_{\mathrm{sep}}:{0,1}^5\to{0,1}^5 be the Boolean 5-ary multimorphism from Živný-Cohen-Jeavons, Fig. 2 / Theorem 16.
Then for every t\ge 1,
Equivalently: the whole size-2 multi-parallel-circuit family, including the first connected \chi\ge 3 cases t\ge 3, survives the direct higher-arity F_{\mathrm{sep}} necessary condition for hidden-vertex graph-cut expressibility.
This is a derived exact finite-state theorem.
- By [[multiple-parallel-classes-on-one-circuit-give-connected-cut-rank-at-least-three-family.md]],
where u(x)\in\{0,1\} is the bit on the singleton element u, and p_i(x)\in\{0,1,2\} is the number of selected elements in P_i.
2. Fix any 5 input assignments x^{(1)},\dots,x^{(5)}. For one class P_i=\{a_i,b_i\}, the whole input-output behavior under F_{\mathrm{sep}} is determined by the two input columns
on a_i,b_i, together with the two output columns
- For such a class, record the masks
and the split-defect
where I_{\mathrm{split}} and O_{\mathrm{split}} are the masks on which the two class bits differ.
4. Enumerating all 32^2=1024 input column pairs (α,β) produces only 402 distinct class summaries
- For
tclasses, only the unions
and the total split-defect
matter. Define a dynamic-programming table that assigns to each union state
the maximum achievable D_t.
6. Exact enumeration gives the following reachable-state counts:
for t=1,2,3,4,5, and the DP reaches a fixed point at t=5, meaning the t=6 table is already identical to the t=5 table.
7. For the singleton element u, let U_1,U_0 be the input masks on which the u-bit is 1,0, and let V_1,V_0 be the corresponding output masks after applying F_{\mathrm{sep}}.
Then the full multimorphism defect is
- Exhaustive evaluation over all
32input patterns onuand all reachable DP union states gives
for each t=1,2,3,4,5.
9. Since the DP has already stabilized at t=5, the same maximum remains 0 for all t\ge 6.
Therefore F_{\mathrm{sep}}\in \operatorname{Mul}(\{f_t\}) for every t\ge 1.
As an internal consistency check on the local page-image decode of Fig. 2, the same reconstructed F_{\mathrm{sep}} reproduces Proposition 18 of Živný-Cohen-Jeavons: the quasi-indecomposable function \theta_{(1,1,0,0)} has a direct F_{\mathrm{sep}} violation with defect 1.
Consequences for the current frontier:
- [[smallest-connected-multi-parallel-circuit-member-survives-all-four-ary-exact-minors.md]] is not the end of the low-arity story: even the direct higher-arity
F_{\mathrm{sep}}test still does not separate this connected family; - the first connected
\chi\ge 3regime therefore survives the selector quotient obstruction, the one-branch-bit local-gadget obstruction, the full exact4-ary closure toolkit, and now also the direct higher-arityF_{\mathrm{sep}}test on an infinite subfamily; - this still does not prove hidden-vertex graph-cut representability for the family, because
F_{\mathrm{sep}}remains only a necessary condition.
Dependencies¶
- [[multiple-parallel-classes-on-one-circuit-give-connected-cut-rank-at-least-three-family.md]]
- [[smallest-connected-multi-parallel-circuit-member-survives-all-four-ary-exact-minors.md]]
- [[selected-or-selector-is-not-hidden-vertex-graph-cut-expressible.md]]
Conflicts/Gaps¶
- This node does not prove a hidden-vertex realization for the multi-parallel-circuit family.
- The theorem is proved only for the subfamily with all
|P_i|=2; it does not cover arbitrary parallel-class sizes. - The argument is derived from exact finite-state computation using the
F_{\mathrm{sep}}operation read from the local Živný page image, not from a verbatim theorem statement in the literature. - Even a future positive hidden-vertex theorem for this connected family would still need a separate bridge to routing-style
CD(T_n,G)semantics.
Sources¶
10.1016/j.dam.2009.07.00110.48550/arXiv.2109.14599Kashyap 2008 preprint: A Decomposition Theory for Binary Linear Codes